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NEW QUESTION: 1
A university has implemented VMware View for classroom labs around the campus. The View administrator needs to ensure that students only print to the printer located in the lab.
Each lab has a dedicated printer.
Which View feature meets these requirements?
A. Central-based printing
B. Local-based printing
C. Location-based printing
D. ThinPrint-based printing
Answer: C

NEW QUESTION: 2
What is the name of the core-to-core transport mechanism used in Intel XEON processors?
A. Quick Path Interconnect
B. Crossbar switch
C. Northbridge
D. Hyper Transport
Answer: A
Explanation:
The way I understand it, Crossbar is not a technology name, but a switch that assist in communication between processors, memory etc, allowing inter core & inter CPU communication. QPI, FSB & HT are all types of connections, connected to crossbar switches. All the answers are connected to crossbards, but only Intel has QPI. I would still go with QPI
www.site.uottawa.ca/~mbolic/ceg4131/Report Crossbar switches.pdf
A. Intel Xeon 7500 architecture The Intel Xeon 7500 series processor architectures uses an 8 port crossbar switch which implements the Intel QuickPath Interconnect (QPI) and routing layers. The Intel QPI is point-point interconnection link developed by Intel [1] to compete with HyperTransport. Prior to using QPI the Intel architecture was using the Front Side Bus (FSB) [2] which was the bus that carried data between CPU and the memory controller (northbridge) and I/O controller(southbridge).
The off-chip single memory controller often was the bottleneck which prevented faster CPUs from improving the overall performance of the system. Now, with crossbar implementation the microprocessor were able to integrate the northbridge on-chip for faster access As well: (Thanx MaaShar from Belgium)
http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology- general.html
Intel@ QuickPath Technology uses Intel@ QuickPath Interconnect, which provides high-speed, point-to-point links inside and outside of the processor. In contrast to parallel buses, these links speed up data transfers by connecting distributed shared memory, the internal cores, the I/O hub, and other Intel@ processors.

NEW QUESTION: 3

A. Option B
B. Option C
C. Option D
D. Option A
E. Option F
F. Option E
Answer: A,B
Explanation:
http://www.oracle.com/technetwork/fusion-apps/productinfomgt-e22709-02-1514575.pdf

NEW QUESTION: 4
How doen MSTP provide backward compatibility with RSTP?
A. It trannmitn all npanning-tree information in one BPDU.
B. It unen the hop count variable an a TTL counter.
C. It encoden the MSTP-npecific region information before the legacy RSTP BPDU.
D. It nupportn up to 128 MSTI mennagen.
Answer: C